1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same in which a difference is made between adjacent circuit regions in the thickness of the same conductivity type epitaxial layer with low impurity concentration formed on a high impurity concentration of a buried semiconductor layer.
2. Description of the Background Art
A random access memory which employs a bipolar transistor preferably has a measure of large collector-base junction capacitance of a transistor which constitutes a memory cell in order to prevent information inversion by radioactive rays, which is called a software error. On the other hand, a transistor which constitutes a peripheral circuit for determining the operating speed of the memory preferably has small collector-base junction capacitance from the viewpoint of the achievement of high-speed operation.
FIG. 5 is a cross-sectional view of an example of conventional semiconductor devices formed to satisfy both of the above mentioned conditions. In FIG. 5, a high impurity concentration of an n.sup.+ buried semiconductor layer 2 is formed on a p.sup.- semiconductor substrate 1. On the n.sup.+ buried semiconductor layer 2 is formed a low impurity concentration of an n.sup.- epitaxial layer 3. The epitaxial layer 3 is adapted to be relatively thin in a memory cell region and relatively thick in a peripheral circuit region. The memory cell region and the peripheral circuit region are divided into a plurality of element regions by groove-type isolating layers 5. In predetermined element regions, p diffusion layers 4 are formed on the surface of the n.sup.- epitaxial layer 3. The n.sup.- epitaxial layer 3 acts as a collector of a transistor, and the p diffusion layers 4 act as bases thereof.
Assuming that the p diffusion layers 4 in the memory cell region are as deep as the p diffusion layers 4 in the peripheral circuit region, the distance between the p diffusion layers 4 and the n.sup.+ buried semiconductor layer 2 is short in the memory cell region, compared with the distance therebetween in the peripheral circuit region. Accordingly, the depletion layer width of the collector-base junction is small in the memory cell region, compared with the depletion layer width thereof in the peripheral circuit region. As a result, collector-base junction capacitance C.sub.1 in the memory cell region can be increased while collector-base junction capacitance C.sub.2 in the peripheral circuit region is held small.
With reference to FIGS. 6A to 6F, a method of manufacturing the semiconductor device of FIG. 5 is described hereinafter. As shown in FIG. 6A, n impurity ions are injected onto the surface of the p.sup.- semiconductor substrate 1. The injected impurities are thermally diffused to form the n.sup.+ buried semiconductor layer 2. Subsequently, as shown in FIG. 6B, the n.sup.- epitaxial layer 3 is grown on the buried semiconductor layer 2. As shown in FIG. 6C, an oxide film 101 is formed on the epitaxial layer 3. On the oxide film 101 is formed a nitride film 102 only in the peripheral circuit region.
As shown in FIG. 6D, masked with the nitride film 102, selective oxidation is performed to thereby form an oxide film 103 in the memory cell region. Hence, the n.sup.- epitaxial layer 3 is made thinner in the memory cell region. It is well known that the thickness of the oxide film 103 is required to be about 1/0.45 times the thickness of the thinned n.sup.- epitaxial layer 3, in the case that the n.sup.- epitaxial layer 3 is made of silicon. As shown in FIG. 6E, the nitride film 102 and the oxide films and 103 are entirely removed. A stair formed on the surface of the n.sup.- epitaxial layer 3 is used as an alignment mark in a later step. After the step of FIG. 6E, the groove-type isolating layers 5 with the depth from the surface of the n.sup.- epitaxial layer 3 to the p.sup.- semiconductor substrate 1 are formed, as shown in FIG. 6F. For example, in this step, the stair is used for the alignment of a photomask for transferring a groove pattern. Subsequently. the element regions which have been isolated from each other by the groove-type isolating layers 5 are, as required, formed with transistors, so that the structure of FIG. 5 is achieved.
In the prior art, the n.sup.- epitaxial layer 3 is reduced in thickness in the memory cell region to be thinner than the n.sup.- epitaxial layer 3 in the peripheral circuit region for the purpose of increasing the collector-base junction capacitance of the transistor in the memory cell region in comparison with the collector-base junction capacitance thereof in the peripheral circuit region. Accordingly, the stair is generated on the surface of the n.sup.- epitaxial layer 3 between the memory cell region and the peripheral circuit region. This surface stair of the epitaxial layer 3 is necessary as the alignment mark in the later step, however, causes the following problems described below.
When a photoresist layer is applied by a spin coater, the photoresist on the lower step in the vicinity of the stair is thicker than the photoresist in the other regions. The lower step in the vicinity of the stair is different from the other regions in the pattern dimension of the photoresist after exposure and development. FIG. 7 is a cross-section view of a semiconductor device illustrating an example of such problems. After the formation of an insulating film 6 on the n.sup.- epitaxial layer 3, a photoresist layer 7 coats the insulating film 6 by the spin coater, and is exposed and developed according to a desired aperture pattern to form apertures in the insulating layer 6, so that the structure FIG. 7 is achieved. As shown in FIG. 7, the thickness R.sub.2 of the photoresist layer 7 on the lower step in the vicinity of the stair of the n.sup.- epitaxial layer 3 is large in comparison with the thicknesses R.sub.1 and R.sub.3 thereof on the lower and upper steps far apart from the stair. Accordingly, the pattern dimension after the exposure and development, that is, a pattern width S.sub.2 at the portion with the thickness R.sub.2 is small in comparison with pattern widths S.sub.1 and S.sub.3 at the portions with the thicknesses R.sub.1 and R.sub.3. As a result, there has been a problem that a desired aperture width cannot be achieved at the portion with the thickness R.sub.2 when the insulating film 6 is etched, masked with the photoresist film 7, to form the apertures.